The present invention relates to buck converters, such as multi-phase buck converters for use in low voltage/high-current applications.
Various applications may provide a conventional DC-to-DC buck converter that accepts a DC input voltage and produces a lower DC output voltage to drive at least one circuit component. Buck converters are typically used in low voltage applications requiring high amounts of load current (e.g., 30 amps or more). Typically, as shown in FIG. 19, a single phase buck converter 1900 includes a high-side switch 1905, a low-side switch 1910 connected to the high-side switch at a switch node 1915, an output inductor 1920 connected to the switch node 1915, and an output capacitor 1925 connected to the output inductor 1920.
In operation, the high-side and low-side switches 1905, 1910 are controlled by a control circuit 1930 to produce a desired output voltage across a load 1935. For this purpose, the high-side switch 1905 is initially switched on, while the low-side switch 1910 remains off. This causes a voltage drop across the output inductor 1920 of approximately (VINxe2x88x92VOUT), which causes a current to build inside the output inductor 1920. At a subsequent time, the high-side switch 1905 is switched off, and the low-side switch 1910 is switched on. Since the current within the inductor 1920 cannot change instantly, sourced through switch 1910, the current continues to flow through the output inductor 1920, thereby charging the output capacitor 1925 and causing the voltage (VOUT) across the output capacitor 1925 to rise.
In this manner, the high-side and the low-side switches 1905, 1910 may be suitably switched at appropriate times, until the voltage (VOUT) across the output capacitor 1925 equals a desired output voltage, which is typically lower than the input voltage. Once the desired output voltage is reached, the high-side and the low-side switches 1905, 1910 may be periodically controlled so that the output inductor 1920 provides an amount of current equal to the current demand of a load 1935 connected across the output capacitor 1925. By providing no more and no less than the current demand of the load 1935, the voltage (VOUT) across the output capacitor 1925 remains at least approximately constant at the desired output voltage.
It is also known to provide a multi-phase DC-to-DC buck converter 2000 including a plurality of interleaving output phases 2005a, 2005b, 2005c, . . . , 2005n, as shown in FIG. 20. As shown in FIG. 20, each of the output phases 2005a, 2005b, 2005c, . . . , 2005n is assigned a respective switching arrangement, including a high-side switch, a low-side switch, and an output inductor. In operation, the control circuit 2010 periodically operates the output phases 2005a, 2005b, 2005c, . . . , 2005n in a time-delayed sequence.
By operating the output phases 2005a, 2005b, 2005c, . . . , 2005n in a phase-delayed sequence, the conventional multi-phase buck converter 2000 distributes current production across the multiple output phases 2005a, 2005b, 2005c, . . . , 2005n, thereby distributing heat generation and reducing the requirements for the output capacitor 1925, such that a smaller output capacitor 125 may be utilized.
However, since conventional multi-phase buck converters require a fixed number of point-to-point connections between the control circuit 2010 and the output phases 2005a, 2005b, 2005c, . . . , 2005n, conventional multi-phase buck converters do not provide a robust architecture capable of easy expandability to include any number of desired phases.
Furthermore, conventional multi-phase buck converters do not optimally control the output voltage in response to a request for a lower desired output voltage or a decrease in current demand of the load 1935. By not optimally controlling the output voltage, conventional multi-phase buck converters may produce unwanted voltage spikes, which may damage circuitry connected to the output of the buck converter.
It is an object of the present invention to provide a multi-phase buck converter that overcomes the disadvantageous of prior art buck converters described above. To achieve this object, the present invention provides a multi-phase buck converter for producing an output voltage to a load, the output voltage being produced from an input voltage in accordance with a desired voltage, the converter including an output capacitor, the output voltage being provided by the output capacitor; a plurality of output switch arrangements having respective output inductors coupled to the output capacitor, the switch arrangements being controllable to provide respective phase output currents to the output capacitor through the respective output inductors; a plurality of phase output arrangements respectively coupled to the output switch arrangements, the phase output arrangements being controllable to set the respective phase output currents supplied by the output switch arrangements; a phase control bus communicatively coupled to each of the phase output arrangements; and a phase control arrangement communicatively coupled to the phase control bus, the phase control arrangement being configured to control the phase output arrangements to set the respective phase output currents supplied by the output switch arrangements so that the output voltage approximates or is regulated to the desired voltage, in which the phase control arrangement and the phase output arrangements are provided as respective integrated circuits, and the phase control arrangement is configured to control the phase output arrangements via the phase control bus.
By separating the functions of the phase control arrangement and the phase output arrangements, an exemplary multi-phase buck converter according to the present invention contains no unused or redundant silicon, since the buck converter may include only those number of phase output arrangements required for a particular application. Thus, if a design engineer requires, for example, a three-phase buck converter for a particular application, the engineer may design the multi-phase buck converter to include only three phase output arrangements, each of which is assigned to a respective one of the three phase outputs. Furthermore, the phase control bus (e.g., a 5-wire analog bus) permits the multi-phase buck converter of the present invention to communicate with a potentially unlimited number of phase output arrangements, without requiring point-to-point electrical connections between the phase control arrangement and each of the phase output arrangements. In this manner, the multi-phase buck converter permits an efficient and easily scalable phase architecture.
In accordance with another exemplary embodiment of the present invention, the multi-phase buck converter is provided with a phase error detect arrangement configured to produce a phase error signal if a phase output arrangement is incapable of providing a phase output current to match the average inductor current of the phase output arrangements. In this manner, the phase control arrangement is provided with a signal for detecting a defective phase and, if appropriate, may deactivate the defective phase and/or enable a back-up phase output arrangement.
In accordance with yet another exemplary embodiment of the present invention, each of the output phase arrangements operates to switch off both the high-side and low-side switches in response to a request for a lower desired output voltage (VDES) or a decrease in current demand of the load. In this manner, the slew rate of the inductor is increased, which enhances the response time of the multi-phase buck converter of the present invention and prevents disadvantageous negative currents from flowing through the output inductor and possibly damaging the power supply.
In accordance with still another exemplary embodiment of the present invention, each of the output phase arrangements includes a current sense amplifier, a resistor RCS electrically connected between the positive input of the current sense amplifier and an output inductor node, and a capacitor CCS electrically connected between the positive and negative inputs of the current sense amplifier, with the output inductor also being connected to the negative input of the current sense amplifier.
By connecting resistor RCS and capacitor CCS across the nodes of the output inductor, the current flowing through the output inductor 220 may be sensed by selecting resistor RCS and capacitor CCS such that the time constant of resistor RCS and capacitor CCS equals the time constant of the output inductor 220 and its DC resistance (i.e., inductance L/inductor DCR, where DCR is the inductor DC resistance), the voltage across capacitor. In this manner, this embodiment of the present invention permits each of the output phase arrangements to sense the current provided to the load in a lossless manner (i.e., without interfering with the current provided to the load).
In accordance with yet another exemplary embodiment of the present invention, the phase control arrangement includes droop circuitry configured to reduce the output voltage in proportion to the current demand of the load. In this manner, this exemplary embodiment permits an efficient and simple method to adaptively modify the output voltage via adaptive voltage positioning.
In accordance with yet another exemplary embodiment of the present invention, each of the phase output arrangements of the multi-phase buck converter is programable to shutdown the high-side and low-side switches of its respectively assigned output switch arrangement as a function of the output current of the multi-phase buck converter. In this regard, the number of phase output arrangements chosen for a particular design may depend upon the need to meet thermal requirements and/or to minimize the number of input and output capacitors at maximum output current. However, at times when the output current of the buck converter is less than the maximum output current, efficiency will increase if less phase output arrangements are employed. Turning off phase output arrangements as the output current decreases, increases efficiency by eliminating the gate charging loses, MOSFET switching losses, and circulating currents in high-side and low-side switches, and the output inductors of each phase output arrangement. Each unique circuit design should turn off phase output arrangements in sequence at particular output current levels to achieve the maximum efficiency over the entire output current range.